A typical CMOS portion (a complementary insulated-gate field effect transistor) of a BiCMOS semiconductor apparatus which has a double-well (twin-tub) structure is shown in FIG. 18. The CMOS portion is comprised of an N+-type buried layer 2 formed on a P-type substrate 1; an N-type epitaxial layer 3 grown over the buried layer 2; an isolated element island isolated by a P+-type isolation layer 4 which reaches the P-type substrate 1; and double wells (a P-type well 5 and an N-type well 6) formed in the isolated element island by ion-implantation and subsequent diffusion. A CMOS transistor is formed in the CMOS portion after the double-well formation. An active region is first covered, for example, by a nitride film, and then an element-isolating insulative film (local oxidation film: LOCOS) 7 is formed on the P+-type isolation layer 4 and the non-well portions between the P- and N-type wells 5 and 6 by selectively oxidizing the nitride film 7. An ion-implanted layer 8 is formed by implanting acceptor type (P-type) impurities, such as BF.sub.2, shallowly from the major faces of the wells 5 and 6. Poly-silicon gate electrodes 10 are then formed on the gate insulation film 9 deposited on the wells 5 and 6. An N+-type source region 11.sub.NS and an N+-type drain region 11.sub.ND are formed by self-alignment using the gate electrode 10 on the P-type well 5 as a mask. Through this step, an N+-type well-contact region 11.sub.NCON is formed simultaneously on the source side in the N-type Well 6. A P+-type source region 11.sub.PS and a P+-type drain region 11.sub.PD are then formed by the self-alignment technique using the gate electrode 10 on the N-type well 6 as a mask. Through this step, a P+-type well-contact region 11.sub.PCON is formed simultaneously on the source side in the P-type well 5. An inter-layer insulation film 12 is subsequently formed. Finally, source electrodes 13.sub.NS, 13.sub.PS and drain electrodes 13.sub.ND, 13.sub.PD, which fill contact holes punched through the insulation film 12, are deposited.
FIGS. 19 and 20 show structures of a high-withstand voltage DMOS portion (double-diffusion type insulated gate field effect transistor) as a power MOS portion of the BiCMOS semiconductor apparatus. A P-type well 5 and an N-type well 6 of the N-channel type DMOSFET shown in FIG. 19 are formed through similar processes to those described above for the CMOS portion. The N-type well 6 constitutes an offset region which functions as an expanded drain for reducing the ON-resistance of the MOSFET.
An active region is covered, for example, by a nitride film, and then an element-isolating insulative film (local oxidation film: LOCOS) 7 is formed over the P+-type isolation layer 4 and thick local oxidation film 7a on the P-type well side on the N-type well 6 by selectively oxidizing the nitride film. An ion-implanted layer 8 is formed by implanting acceptor type (P-type) impurities, such as BF.sub.2, shallowly from a major face of the P-type well 5. A gate electrode 10 is formed on gate insulation film 9 deposited on the P-type wells 5. A P-type base region (channel diffusion region) 21 is self-aligned in the P-type well 5 more deeply than the diffusion depth of the ion-implanted layer 8 by employing a process for forming a P-type base region of a bipolar transistor (NPN transistor) described later and by using the gate electrode 10 as a mask. An N+-type source region 22.sub.NS is then formed from a major face side of the P-type base region 21 by employing the process for forming the N+- drain and source of the CMOS portion and by double diffusion using the gate electrode 10 as a mask, and an N+-type well-contact (drain) region 22.sub.NCON from a major face of the N-type well 6. An inter-layer insulation film 12 is formed. Finally, a source electrode 23.sub.NS and a drain electrode 23.sub.ND, which fill contact holes punched through the insulation film 12, are deposited. The thick local oxidation film 7a contributes to the provision of a higher withstand voltage by relaxing the electric field convergence onto the edge of the drain.
A P-type well 5 and an N-type well 6 of the P-channel type DMOSFET of the DMOS portion shown in FIG. 20 are formed through similar processes to those for the CMOS portion and the P-type well 5 constitutes an offset region which functions as an expanded drain for reducing ON-resistance of the MOSFET. At first, an active region is covered, for example, by a nitride film, and then element-isolating insulative film 7 is formed on the P+-type isolation layer 4 and thick local oxidation film 7a on the N-type well side on the P-type well 5 by selectively oxidizing the nitride film. An ion-implanted layer 8 is formed by implanting acceptor type (P-type) impurities, such as BF.sub.2, shallowly from a major face of the N-type well 6. A gate electrode 10 is formed on the gate insulation film 9 deposited on the N-type wells 6. A P+-type source region 22.sub.PS is self-aligned in the N-type well 6 on from its major face more deeply than the diffusion depth of the ion-implanted layer 8 by employing the process for forming the P+-type source and drain of the CMOS portion and by using the gate electrode 10 as a mask, and P+-type well-contact region 22.sub.PCON in the P-type well 5. Inter-layer insulation film 12 is then formed. Finally, a source electrode 23.sub.PS and a drain electrode 23.sub.PD which fill contact holes punched through the insulation film 12 are deposited. The thick local oxidation film 7a contributes to provision of higher withstand voltage by relaxing the electric field convergence onto the edge of the drain.
The bipolar transistor portion of the BiCMOS semiconductor apparatus is comprised of a vertical NPN transistor and a transverse PNP transistor as shown in FIG. 21. The bipolar transistor portion is formed through processing steps similar to those for forming the CMOS portion as follows. At first, an N+-type buried layer 2 is formed on a P-type substrate 1. An N-type epitaxial layer 3 is grown over the buried layer 2, and a P+-type element isolation layer 4, which reaches the substrate 1, is then formed to isolate an element island. In fabricating the vertical NPN transistor, a P-type base region 31.sub.PB is formed in the N-type epitaxial layer 3. An N+-type emitter region 32.sub.NE and an N+-type collector region (collector-contact region) 32.sub.NC are then formed by employing the process for forming the N+-type source and drain of the CMOS portion. After forming inter-layer insulation film 12, a base electrode 33.sub.B, an emitter electrode 33.sub.E, and a collector electrode 33.sub.C, which fill contact holes punched through the insulation film 12, are formed. In fabricating the transverse PNP transistor, a P-type emitter region 31.sub.PE and a P-type collector region 31.sub.PC are formed in the N-type epitaxial layer 3 by employing the process for forming the P-type base region 31.sub.PB of the vertical transistor. A N+-type base region (base-contact) 32.sub.NB is then formed by employing the process for forming the N+-type source and drain of the CMOS portion. After forming inter-layer insulation film 12, a base electrode 34.sub.B, an emitter electrode 34.sub.E, and a collector electrode 34.sub.C, which fill contact holes punched through the insulation film 12, are formed.
The N-channel DMOSFET with double-well structure shown in FIG. 19, which functions as the power DMOS portion, may be constructed in a DMOS structure shown in FIG. 22 from which the P-type well 5 and the ion-implanted layer 8 are eliminated. In fabricating the N-channel DMOSFET of FIG. 22, an N+-type buried layer 2 is formed on a P-type substrate 1. An N-type epitaxial layer 3 is grown over the buried layer 2. A P+-type element isolation layer 4, which reaches the substrate 1, is then formed to isolate an element island. An N-type well 6 is formed in the isolated element island by ion-implantation and subsequent diffusion. The N-type well 6 functions as an offset region as an expanded drain for reducing ON-resistance of the MOSFET. An active region is covered, for example, by nitride film, and element-isolating insulative film 7 is then formed on the P+-type isolation layer 4 and thick local oxidation film 7a is formed on the edge portion of the N-type well 6 by selectively oxidizing the nitride film. A gate electrode 10 is formed on gate insulation film 9 deposited on the N-type epitaxial layer 3. A P-type base region (channel diffusion region) 21 is then formed, as described earlier, by employing the process for forming the P-type base of the bipolar transistor (NPN transistor), by implanting impurity ions from a major face of the N-type epitaxial layer 3 by the self-alignment technique using the gate electrode 10 as a mask, and by subsequent heat treatment between 1000.degree. and 1200.degree. C. An N+-type source region 22.sub.NS is then formed from a major face of the P-type base region 21 by employing the process for forming the N+-type drain and source of the CMOS portion, and by ion-implantation using the gate electrode 10 as a mask followed by subsequent double diffusion. At the same time, an N+-type well-contact region 22.sub.Ncon is formed from a major face of the N-type well 6. After depositing inter-layer insulation film 12, a source 23.sub.NS and a drain electrode 23.sub.ND, which fill contact holes punched through the insulation film 12, are then formed. Finally, a passivation film is deposited. The thick local oxidation film 7a contributes to provision of higher withstand voltage by relaxing electric field convergence onto the edge of the drain.
The BiCMOS structure according to the prior art which is comprised of the above described DMOS portion as the power MOS portion has a number of deficiencies. For example, in the high-withstand voltage DMOS portions shown in FIGS. 19 and 20, the ion-implanted layers 8 are formed by employing the ion-implantation process for forming the ion-implanted layer of the low-withstand voltage CMOS. Since ion-implantation process exclusive for forming an ion-implanted layer of the DMOS portions is not employed, the P-type ion-implanted layers 8, especially that of the N-channel MOSFET shown in FIG. 19, tends to be subject to an insufficient withstand voltage caused by surface punch through because of a deficit in the amount of total acceptors. Elongated channel length for avoiding this problem increases ON-resistance, which is hazardous for increasing current capacity. Withstand voltage increase and ON-resistance decrease are therefore in a trade-off relation to each other.
In the DMOS structure shown in FIG. 22, the P-type base region 21 is formed by ion-implantation from the major face of the N-type epitaxial layer 3 using the gate electrode 10 as a mask for self-alignment and by heat treatment at a high temperature for a long period of time. Therefore, the process for forming the P-type base region 21 of FIG. 22 requires an increase in the number of processing steps. Moreover, since impurities diffuse from the gate electrode 10 into the gate insulation film 9 and the channel portion in the surface of the P-type base region 21 during the heat treatment, the impurity concentration distribution (acceptor in N-type MOS and donner in P-type MOS) cannot be accurately controlled. This further causes an unstable threshold voltage and difficulty in securing a withstand voltage because of a deteriorated reliability of the gate insulation film 9. In addition, since the too deep diffusion depth of the P-type base region 21, formed by the heat treatment at high temperature for long period of time causes elongated effective channel length of the MOSFET, i.e. channel resistance (ON-resistance) increase, current capacity increase is hindered.
Though the diffusion is confined within a shallow depth when the heat treatment at high temperature for a long period of time is not applied, the dose amount of implanted impurity should be increased instead, which causes increased crystal defects in the channel portion which further causes deterioration of yield of the non-defective element, especially of a large area. Since a PN junction between the P-type base region and 21 and the N+ type source region 22.sub.NS is formed in the channel surface region in which the transverse impurity concentration gradient in the P-type base region is large, dispersion of the N+ diffusion depth causes dispersion of surface concentration in the P-type base region, which further causes dispersion of the threshold voltage.
In view of the foregoing, a first object of the present invention is to provide a manufacturing method which facilitates increasing the withstand voltage and current capacity of a DMOS portion of a BiCMOS semiconductor apparatus. A second object of the present invention is to provide a manufacturing method which facilitates eliminating processes exclusive for forming the DMOS portion and forms the DMOS portion solely through the BiCMOS processing steps. A third object of the present invention is to provide a manufacturing method which facilitates suppressing crystal defect formation in the channel portion and forming the highly reliable DMOS portion. A fourth object of the present invention is to provide a manufacturing method which facilitates suppressing dispersion in the characteristics of the pertinent portions which affect the threshold voltage of the DMOS portion. Other objects and advantages will become apparent from the following detailed discussion of the preferred embodiments of the invention.